Bus access request - HOLD,HLDA in minimum mode

Question 


In minimum mode of microprocessor 8088, HOLD and HLDA pin are used to control the bus system access by both CPU and I/O devices. Draw simplified data/wave form for HOLD, HLDA and bus access pin/device.

Answer

Bus access request - RQ/GT' maximum mode

Question

Explain how external chip/IO devices request and control the system bus in maximum mode. Draw the corresponding timing diagram.

Answer

In maximum mode, the RQ'/GT' (request and grant) pin will play the important role. Whenever a device want access to the system bus, the device will lower RQ'/GT' for one cycle to request the access. After receiving the request, 8086/8088 will grant the access to system bus by also lowering the RQ'/GT' pin for one cycle.

Note that even though it is the same pin that being lowered at both occasion, the purpose is different

Request --> RQ' = 0' = 1= requesting access
Grant --> GT' = 0' = 1 = granting access

Read cycle timing diagram in minimum mode

Question

Draw a simplified timing diagram for a read cycle of the 8088 microprocessor (minimum mode). The diagram should include at least the following
i.    Address pin
ii.    Address/Data pin
iii.    WR' pin
iv.    CLK timing
v.    ALE pin
 
 Answer

READY pin function in 8284A Clock Generator chip

Question

Briefly describe the function of READY pin in 8284A clock chip in relation to synchronization with other I/O or memory.

Answer
The ready pin generates the Ready signal for the 8086/8088. Usage example can be seen in the following READ and WRITE cycle where the important process only started after READY pin is set.

8284 Clock Generator using an external source for its frequency

Question
Modify the following  8284A clock generator circuit if it will be using an external frequency from another source.

Answer

EFI - changed from earth to the OSC input from other 8284A (EFI=external frequency input)
F/C' - changed from earth to Vcc (5v) because now the chip is using F(requency) input instead of C(rystal) input
Both X1 & X2 - grounded

Illustrated here

Calculate CLK & PCK frequency of a 8284A clock generator

Question

Given in the following diagram is a simple 8284A clock generator circuit that uses a 15MHz crystal input. Calculate the corresponding CLK and PCLK frequency. 

8284A with 15Mhz crystal diagram

Answer

CLK = 33% crystal/EFI = 0.33 (15Mhz) = 5 Mhz
PCLK = 50% crystal/EFI = 0.5 (15Mhz) = 7.5Mhz

IP and FLAG register's function

Question
What are the functions of IP and FLAG register?

Answers

Flag register - Flag register function is to record few parameter or characteristic from the last aritmetic/logic instruction. Flag register include zero flag,parity flag,carry flag,auxiliary carry flag, sign flag and overflow flag

IP register - IP is Instruction Pointer. Its function is the same as PC (program counter) in other microprocessor which is to point to the next instruction to be fetched by BIU unit to be feed into EU unit.

Read/Write bus cycle difference in minimum and maximum mode

Question
Given in the diagram below is the 8088 chip and 8288 chip connection in maximum mode. Explain the read / write difference between maximum and minimum mode operation in 8088 chip.

 Diagram: Maximum mode connection

Table: 8288 Command Table

Answer
 In minimum mode, the read and write command signal are generated by 8088 using the WR' and RD' pin.

In maximum mode, the control signal to read and write are generated by external chip which is 8288. The corresponding command include MRDC' (for read) and MWTC (for write).

The following two diagram depic the difference for Read bus cycle in both minimum and maximum mode.

Difference between minimum & maximum mode from control signal perspective

Question
What is the difference between minimum and maximum mode from the control signals perspective?

Answer
In minimum mode, all control signals are self generated by 8086/8088 microprocessor such as RD' and WR'.

In maximum mode, the control signals are generated by external chip such as MRDC' (memory read) and MWTC' (memory write) by 8288 chip.

8284A Clock Generator Output (CLK,Ready,Reset) tutorial

Question
There are 3 output generated by 8284A clock generator that is connected into 8088 microprocessor. Explain its function.

Answer
The 8284A clock generator consist of a synchronous divide-by-three counter. It has several output including CLK,PCLK,OSC,Reset,Ready. Out of this 3 pins are connected to the 8088 microprocessor which is CLK,Reset and Ready.

CLK- This is the clock output used by the processor and other devices that directly using the processor local bus. CLK output is 33% duty cycle clock driver.
RESET- This signal is used to reset the 8086 microprocessor
READY-This signal used to indicate the readiness of the microprocessor. It will be cleared after the guaranteed hold time to the processor has been met.

Address Latch Enable pin (ALE) tutorial

Question

Based on the following ALE waveform, what are the data that flow through AD0-AD7 at cycle T3 until T4.

Answer

AD-AD7 can carry both Address and Data type of data. ALE is the pin that indicate what is the type of data that currently flow through AD-AD7 pin.

ALE = 0 ( address latch disabled --> data )
ALE = 1 ( address latch enabled --> address )


At cycle T3 until T4 ALE=0 therefore the data that flowing through AD0-AD7 is Data.

Bus Interface Unit (BIU) and Execution Unit (EU) tutorial

 Question

The diagram above is the function block diagram for Intel 8088. What are the functions played by the Bus Interface Unit and Execution Unit? How both complement each other.

Answer

Both BIU and EU have their own job specification. BIU is the unit that will oversea data or operand transfer from its original source to EU. EU is the unit that handle operation execution be it arithmetic operation or logic operation.

By separating both function, both can run concurrently therefore would enable pipelining which would expediate microprocessor processing.